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[Other resource] VHDL.fifo

Description: 在网上找到的通用存储器vhdl代码库，觉得挺好用的。-the Internet to find the common memory vhdl code library, feeling very good use.
Platform: | Size: 1178849 | Author: 黎莉 | Hits:

[Embeded-SCM Develop] 通用存储器包括各种类型存储器的VHDL描述

Description: 通用存储器包括各种类型存储器的VHDL描述， 如FIFO，双口RAM等VHDL代码库
Platform: | Size: 617824 | Author: hanker3 | Hits:

[VHDL-FPGA-Verilog] fifo的vhdl原代码

Description: 本文为verilog的源代码-In this paper, the source code for Verilog
Platform: | Size: 22528 | Author: 艾霞 | Hits:

[VHDL-FPGA-Verilog] fifo_vhd

Description: vhdl编写的fifo程序-VHDL procedures prepared by the fifo
Platform: | Size: 1024 | Author: 李冬梅 | Hits:

[VHDL-FPGA-Verilog] 一些VHDL源代码

Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: | Size: 45056 | Author: 蔡孟颖 | Hits:

[VHDL-FPGA-Verilog] VHDL 的实例程序，共44个

Description: 经典VHDL 的实例程序，共44个！要下载的尽快-classic examples of VHDL, with a total of 44! To download as soon as possible
Platform: | Size: 43008 | Author: 立立 | Hits:

[VHDL-FPGA-Verilog] 异步FIFO存储器的控制设计

Description: 异步FIFO控制器的设计 主要用于异步先进先出控制器的设计。 所用语言Verilog HDL.-asynchronous FIFO controller design for the main asynchronous FIFO controller design. The language used Verilog HDL.
Platform: | Size: 6144 | Author: 李鹏 | Hits:

[VHDL-FPGA-Verilog] fifo_VHDL

Description: 该文件是先入先出fifo的源代码和测试文件-the document is first-in-first out fifo the source code and test document
Platform: | Size: 7168 | Author: 王立华 | Hits:

[VHDL-FPGA-Verilog] fifo88

Description: 8*8位的先入先出（fifo）数据缓冲器的vhdl源程序-8* 8 of the first-in-first out (FIFO) buffers the data source VHDL
Platform: | Size: 317440 | Author: hailaing | Hits:

[source in ebook] fifo

Description: fifo example vhdl code
Platform: | Size: 1024 | Author: whatisthegame | Hits:

[SCM] FIFO

Description: FIFO中文应用笔记，对学习单片机RAM、大量数据处理很有帮助。-FIFO notes
Platform: | Size: 1136640 | Author: chenlei | Hits:

[VHDL-FPGA-Verilog] fpga.fifo

Description: 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the phase and frequency offset between different clock domain in communication area .In this paper, an FIFO module is designed using Gray convert technology and dual-port ram , which realizing scatheless transmit between different clock domain. The advances of Gray (Only one bit changes between neighboring two clock ) improves the reliability and anti-jamming capability of the system. And the system can work normally in the bad condition which the phase and frequency offset target to 300PPM. It is proved by work that the FIFO module can fulfill the demands of real-time of data transmitting system, and the module is powerful enough for more data process in the future.
Platform: | Size: 81920 | Author: 雷志 | Hits:

[VHDL-FPGA-Verilog] fifo-interface

Description: fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
Platform: | Size: 1024 | Author: sunbaoyu | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
Platform: | Size: 4096 | Author: 邵捷 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 先进先出存储电路fifo，实现队列存储结构-xianjin xianchu chunchu dianlu fifo
Platform: | Size: 489472 | Author: 623902748 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 用VHDL语言写的FIFO代码，可设FIFO的深度-VHDL language with code written in FIFO, FIFO depth can be set up
Platform: | Size: 1024 | Author: wd | Hits:

[VHDL-FPGA-Verilog] fifo

Description: fifo 的vhdl源程序,容量为1024*8的fifo程序代码-fifo the vhdl source code,Capacity of 1024* the fifo code 8
Platform: | Size: 1024 | Author: 谢文华 | Hits:

[Software Engineering] fifo

Description: 异步fifo的经典讲解，包括亚稳态的产生，同步电路的构造，fifo电路的结构，源代码实现。-Asynchronous fifo on the classic, including the emergence of metastable, the structure of synchronous circuits, fifo circuit structure, the source code to achieve.
Platform: | Size: 3224576 | Author: 王玉 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 同步FIFO 创建一个256x8大小的同步FIFO，并通过串口发送数据初始化FIFO，FPGA内部读取FIFO的数据通过窗口发送到PC-FIFO
Platform: | Size: 4096 | Author: 赵云 | Hits:

[Other] fifo

Description: 这是一个用VHDL编写FIFO模块，已经通过测试-fifo
Platform: | Size: 1010688 | Author: 于洋 | Hits:
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